01 May 2008

Why, Intel, why?

This diff is highly related to this post.

If one looks in Intel's documentation of their assembly, one notices a few things. In particular, there are a whole bunch of operations which do exactly the same thing but have different opcodes. Intel introduces "movaps" and "movups" for aligned and unaligned moves in SSE1, and then "movdqa" and "movdqu" in SSE2... to do exactly the same thing. The same situation occurs with pand and andps... etc. The end result is a number of things:
1. Wasted opcode space on opcodes that do exactly the same thing.
2. Wasted executable size, since movdqa is larger than movaps (3 byte vs 2 byte opcode) despite doing exactly the same thing.
3. Loss of our sanity.

2 comments:

Thomas said...

I imagine it has much to do with the development of a cpu. Rather then remake every instruction set, intel is much more likely to "Copy" the circuitry from the last cpu and "Paste" it into new generations.

Perhaps in part of this process they have an SSE1 section and a SSE2 section. The SSE1 section dating back to the orgional P3 (I believe, maybe it was P2) and the SSE2 section being new.

That would be my thoughts on why it was done this way. Maybe there is some underlying difference going on that we just don't see. (fewer gates to hope through for an instruction, I don't know). But this is why I would guess they did it that way. My guess is the transistors added for having the same instruction was not that big of a deal for them.

Abao said...

haha...seems like the organisation doesnt know what they know, hence they recreated the same functions for sse2... -_o